Correct Communication in Multi-Core Processors

Computer chips, the most complex artifacts ever made by man, are
susceptible to problems with correct functionality due to their
intricacy. Incorrect operation of silicon chips has lasting, and
sometimes devastating, effects on computer systems and their
manufacturers: from incorrect computation results, to security
vulnerabilities affecting end users, to financial impact on the
vendors. Furthermore, new chips are increasingly fragile, liable to
break as the transistors that comprise them become small enough to be
measured in atoms.

A typical modern computer usually includes a single chip where many
processors are connected by a communication medium. This
communication medium, a new feature in modern chips, provides many
opportunities for catastrophic errors, as it is a complex,
unpredictable, unique component.

The goal of this dissertation is to provide a new solution to ensure
the correct operation of the communication medium in multicore
processors, from the early stages of design to the end user. It
addresses failures in several modes, and operates across the different
phases of the verification process. Simply put, it ensures that the
design operates as intended. This approach to the development cycle
accelerates, automates and extends the reach of the verification
process, providing decreased occurrence of — and increased
resilience to — failures. With this solution, the communication
system of multi-core chips can operate free from errors.