Faculty Candidate Seminar
Towards Scalable and Reliable Architectures for Quantum Computing Platforms
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Abstract: Quantum computing promises significant speedup for an important class of problems. While quantum computers with few tens of qubits have already been demonstrated and machines with 100+ qubits are expected soon, these machines face significant reliability and scalability challenges. Due to limited and unreliable qubits, these machines are operated in the Noisy Intermediate Scale Quantum (NISQ) mode of computing. The computation on a NISQ machine can produce incorrect output. Therefore, in the NISQ mode, a program is run thousands of times, and the output log is analyzed to infer the correct output. However, the error rates on current quantum hardware are such that the likelihood of obtaining the right answer is still quite small for NISQ machines, and this problem only becomes worse for programs with a large number of instructions.
In this talk, I will discuss some of our recent work that aims to improve the reliability of near-term quantum computers by developing compilation techniques to mitigate hardware errors. Our first work (ASPLOS 2019) exploits the variability in the error rates of qubits to steer more operations towards qubits with lower error rates and avoid error-prone qubits. Our second work (MICRO 2019a) looks at executing different versions of the programs tuned to cause diverse mistakes so that the machine is less vulnerable to correlated errors, thereby making it easier to infer the correct answer. Our third work (MICRO 2019b) looks at exploiting the state-dependent bias in measurement errors (state 1 is more error-prone than state 0) and dynamically flips the state of the qubit to measure the stronger state. We perform our evaluations on real quantum machines from IBM and demonstrate significant improvement in the overall system reliability. If time permits, I will also briefly discuss the control hardware (MICRO 2017) aspect of designing quantum computers, including some of our work on the cryogenic processor and cryogenic memory system.
Bio: Swamit Tannu is a Ph.D. candidate in the School of Electrical and Computer Engineering at
the Georgia Institute of Technology. Where he is advised by Dr. Moinuddin Qureshi, his work
identifies challenges in building quantum computing systems and software. At Georgia Tech, he
is developing compilers and runtime techniques to improve the reliability of noisy quantum
computers. During 2015 to 2019, Swamit worked with Microsoft as Research Intern and
contributed towards building architectural abstractions for quantum and superconducting
accelerators. His work on Superconducting Accelerators won the Best Paper Award at
Computing Frontiers 2019.