Computer Engineering Seminar

Defect Aware Tests

Professor Sudhakar Reddy

Abstract: Two approaches are currently being investigated to derive tests to detect the most likely defects in manufactured VLSI circuits. One is called the Defect Based Test (DBT) generation and the other is called the n-detection test generation. The former approach uses test generation for faults that more accurately model the defects. The latter approach uses classical fault models such as single line stuck-at and transition faults and generates tests that detect each modeled fault n ( n>1) times. DBT approach requires extracting most likely defects from the physical implementation of the circuit under test and then using fault models for the extracted defects to generate tests. Typically DBT requires much longer run times to extract the most likely defects and to generate tests for the more accurate fault models. The effectiveness of the latter approach which typically requires much shorter run time, depends on accidental detection of defects by the tests derived using simpler fault models.

In this talk we present a method to generate tests, called Defect Aware Tests, with improved effectiveness in detecting un-modeled defects. Results of experiments on several industrial designs using n-detection tests show that Defect Aware Tests achieve the same or higher coverage of defects with fewer tests.

Sudhakar M. Reddy received the B.E. degree in electronics and communication engineering from Osmania University, Hyderabad, India, M.E. degree from the Indian Institute of Science, Bangalore, India and the Ph.D. degree in electrical engineering from the University of Iowa, Iowa City, Iowa. Since 1968, he has been a member of the faculty of the Department of Electrical and Computer Engineering, University of Iowa, where he is currently a University of Iowa Foundation Distinguished Professor. He served as the Chair of the Department from 1981 to 2000. Dr. Reddy has published over four hundred papers in the areas of test and design for test of digital VLSI circuits, coding theory and fault-tolerant computing. He is a Fellow of IEEE. He received a Von Humboldt Senior Research Fellowship in 1995 and a life time achievement award from the VLSI Design Conference.

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