Inside Intel Logic Technology Development: Taking SRAM From 32nm Planar to 22nm Tri-gate Technology

Future electronic product applications demand increasing performance with reduced power consumption at a constant or shrinking cost, which
motivates technology scaling that targets high-performance at reduced operating voltages. The electrical benefits of geometric shrinks in advanced process technologies have greatly diminished, and innovation in materials engineering, device architecture and circuit co-optimization are required to provide performance
and power advantages in the future. The role of advanced circuit design teams in driving Intel technology development is highlighted, with a focus on memory circuits. Random and systematic device variations pose significant challenges
to SRAM Vmin and low-voltage performance as technology scaling follows Moore's law to the 22nm node. A high-performance, voltage-scalable 162Mb
SRAM array in a 22nm tri-gate bulk technology featuring 3rd-generation high-k metal-gate transistors and 5th-generation strained silicon is discussed. Processcircuit co-optimization of write and read assist features addresses process variation and fin quantization at 22nm and enables a 175mV reduction in the supply voltage required for 2GHz SRAM operation.
Eric Karl is an Design Engineer in Intel's Logic Technology Development group located in Hillsboro, Oregon, where he is responsible for memory technology development for Intel's advanced logic processes. He joined Intel in 2008 and has been responsible for technology lead vehicle design, memory bitcell development and memory circuit technology pathfinding. Prior to joining Intel LTD,
he worked on circuit design at the IBM T. J. Watson Research Center, Intel Circuit Research Labs and Sun Microsystems. Dr. Karl is currently developing memory bitcells and circuit technology for Intel's 10nm logic technology. In 2012, he received an Intel Achievement Award for work on 22nm memory circuit technology.
Dr. Karl received BSE, MSE, and PhD degrees in Electrical Engineering from the University of Michigan "“ Ann Arbor in 2002, 2004, and 2008, respectively. He has authored or co-authored more than 15 technical papers and holds several patents.