Performance, Power, and Thermal Modeling and Optimization for High-Performance Computer Systems

This dissertation presents several models for performance, power, and thermal estimations in high-
performance computer systems. In addition, it also describes a hardware-oriented cache compres-
sion algorithm, a software-based online dynamic voltage and frequency scaling (DVFS) algorithm,
and a software-based performance maximization technique in a power-constrained CMP environ-
ment, all of which are motivated by the observations obtained when developing the aforementioned
models.
After summarizing the impact of architectural evolutions on various aspects of computer mod-
eling, we present three models that estimate the performance, power, and temperature in such
systems. The first model, CAMP, is a fast and accurate cache aware performance model for chip
multiprocessors (CMPs) that estimates the performance degradation due to cache contention of
processes running on cache-sharing cores. We then propose a system-level power model in a
multi-programmed CMP environment that accounts for cache contention and explain how to in-
tegrate the two models for power estimation during process assignment, helpful for power-aware
assignment. We also describe an IC thermal model and analyze the performance and accuracies of
a variety of time-domain dynamic thermal analysis techniques that build upon the aforementioned
thermal model, which motivates our new thermal analysis technique that significantly improves
performance while maintaining similar accuracy.
When developing the performance model and the power model, we realized that memory hier-
archy is of critical importance to system performance and energy consumption. This observation
inspires the design and implementation of a high-performance microprocessor cache compression
algorithm to expand effective on-chip last-level cache size and improve cache performance. It also
leads to a predictive dynamic voltage and frequency control (DVFS) algorithm that takes advantage
of the performance model and the power model for on-line minimization of energy consumption
under a performance constraint without requiring a priori knowledge of an application’s behavior.
Finally, we propose PerfMax, a performance optimization technique that considers both process
assignment and local power state control in a power-constraint environment for multi-chip CMPs
with chip-wide DVFS based on accurate performance and power models.