Computer Engineering Seminar
High speed CMOS transceivers for parallel optical interconnects
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The increasing speed of on-chip data processing and computation create a growing demand for high-bandwidth input and output (IO) to VLSI circuits. However, increasing the bandwidth of electrical signaling with the same rate is becoming very challenging. The possibility of using optics for interconnection at short distances has been recently a subject of considerable research and analysis. A very promising design platform is to hybrid integrate dense arrays of optical devices (lasers, modulators and detectors) with commercial electronic circuits to establish a very high data rate, parallel link for chip-to-chip interconnection. Such a system requires receiver and transmitter circuitry that is very small and has low power consumption.
This talk describes the design and implementation of CMOS transceivers suitable for parallel optical interconnects with flip-chip-bonded optical devices. The receiver front-end uses a novel double sampling/integrating scheme with 1:5 demultiplexing to avoid having to build a transimpedance amplifier that runs at the bit rate. In this design the optically generated current is integrated onto the parasitic capacitor of the input node and voltage-samples are compared for data recovery. Moreover rather than using the standard 2x oversampled approach for clock recovery, this receiver uses a new baud-rate CDR based only on data samples, to reduce both complexity and power consumption. Our transceiver test chip achieves data rates as high as 5Gb/s and consumes less than 145mW of power per link in a 0.25 µm CMOS technology. At the end, scaling to future technologies and potential extension of these techniques for future research will be briefly discussed.
Azita Emami is a PhD candidate in the department of Electrical Engineering, Stanford University, CA. She received her BS in Electrical Engineering from Sharif University of Technology, Tehran, Iran in 1996, and her MS degree from Stanford University, CA in 1999. She expects to receive her PhD by Spring 2004 under the supervision of Professor Mark Horowitz at the Computer Systems lab, Stanford University. Her research areas are mixed signal integrated circuit and system design, high-speed, low-power optical interconnects, and VLSI systems.