Computer Science and Engineering

Todd Austin earns Test of Time Award for early instruction prefetch breakthrough

The technique turned out to be a significant and long-lasting development for microprocessor design.

Todd Austin Enlarge
Prof. Todd Austin

Todd Austin, the S. Jack Hu Collegiate Professor of Computer Science and Engineering, has been awarded the MICRO Test of Time award for his landmark 1999 paper, “Fetch Directed Instruction Prefetching.” This award recognizes the most influential papers published in prior sessions of the International Symposium on Microarchitecture. The paper outlined fetch directed prefetching, which is foundational to the decoupled CPU frontend, a key building block of many modern CPUs.

Austin’s paper, co-authored with Glenn Reinman and Brad Calder from the University of California, San Diego, introduced the idea of Fetch Directed Instruction Prefetching. Computer processors are typically composed of two engines: the front-end processor and the execution core. It was the front-end processor that concerned the collaborators in this project, which is responsible for fetching and preparing instructions for execution. The execution core carries out the execution of these instructions and retires their memory registry for use by other programs.

Instruction prefetching is a mechanism that was still young at the time of the paper’s publication. It was proposed to help reduce instruction cache misses, in turn helping increase the speed of instruction supply to the processor.

This paper demonstrated an instruction prefetching technique that decoupled the processor’s branch predictor from its instruction cache, allowing the predictor to run ahead of the main thread of execution and provide memory addresses to prefetched instructions before they’re needed. This provides a simple but very effective instruction prefetching technique that allowed the performance of instruction delivery to better scale with execution performance.

The technique turned out to be a significant and long-lasting development for microprocessor design, as well as academic research into instruction prefetching. The paper built on the idea of the Fetch Target Queue introduced previously by the same authors.

“Given today’s ever-expanding instruction working set sizes, we expect this seminal work to become even more important as research into instruction prefetching continues,” ACM SIGARCH wrote in their announcement.

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