Hardware-Software Co-design for Reliable and Efficient Heterogeneous Systems

Virtual Event: Zoom

Abstract: System builders are increasingly turning to heterogeneous systems to accommodate the ever-growing demand of computing. As specialized hardware emerges, it is always important to rethink system design and expand system support to new heterogeneous setups. In the thesis defense, I will talk about my experience of improving reliability and efficiency of heterogeneous systems across the computing stack from applications down to hardware. The main theme is to apply hardware-software co-design from two perspectives:
1) Take a specialized hardware, how to best utilize it to solve an existing problem better?
2) Take a wonderful existing technique, how to adapt it to support new specialized hardware?
First, I will discuss my work on combining symbolic execution with CPU’s tracing accelerator to improve software failure reproduction, which is at the heart of software reliability.  Then, I will cover my work on the CPU/FPGA type of heterogeneous systems, where I built a record/replay framework to recreate FPGA program executions and co-created virtualization support for shared-memory FPGA systems.
Next, I will briefly talk about my experience of customizing the CPU scheduler to distinguish virtualized CPU from physical CPU, which improves virtualization efficiency. At the end, I will discuss ongoing and future work.