Dissertation Defense

Intelligent Management of Inter-Thread Synchronization Dependencies for Concurrent Programs

Hyoun Kyu Cho

ABSTRACT: Power dissipation limits and design complexity have made the microprocessor industry
less successful in improving the performance of monolithic processors, even though semiconductor
technology continues to scale. Consequently, chip multiprocessors (CMPs) have become a standard
for all ranges of computing from cellular phones to high-performance servers. As sufficient thread
level parallelism (TLP) is necessary to exploit the computational power provided by CMPs, most
performance-aware programmers need to parallelize their programs.
For shared memory multi-threaded programs, synchronization mechanisms such as mutexes, barriers,
and condition variables, are used to enforce the threads to interact with each other in the way the
programmers intended. However, employing synchronization operations in both correct and efficient
ways at the same time is extremely difficult, and there have been trade-offs between programmability
and efficiency of using synchronizations.
This thesis proposes a collection of works that increase the programmability and efficiency of
concurrent programs by intelligently managing the synchronization operations. First, we focus on
mutex locks and unlocks. Many concurrency bug detection tools and automated bug fixers rely
on the precise identification of critical sections guarded by lock/unlock operations. We suggest a
practical lock/unlock pairing mechanism that combines static analysis with dynamic instrumentation
to identify critical sections in POSIX multi-threaded C/C++ programs. Second, we present Dynamic
Core Boosting (DCB) to accelerate critical paths in multi-thread programs. Inter-thread dependencies
through synchronizations form critical paths. These critical paths are major performance bottlenecks
for concurrent programs, and they are exacerbated by workload imbalances in performance
asymmetric CMPs. DCB coordinates its compiler, runtime subsystem, and architecture to mitigates
such performance bottlenecks. Finally, we propose exploiting synchronization operations for better
energy efficiency through dynamic power management.

Sponsored by

Scott Mahlke