Computer Engineering Seminar

Multi-Core Microprocessor Chips: Motivation & Challenges

Dileep Bhandarker

Advances in semiconductor process technology allow hundreds of millions of transistors to be integrated on a single chip. Intel has already built the first Billion transistor chip featuring dual cores and a large cache. Intel’s technology investment and prowess continues to drive Moore’s Law to provide a doubling of the transistor density every two years. Multi-core chips have started to emerge not only in high end servers but also in desktop and mobile PCs, and the penetration of multi-core is expected to increase dramatically over the next few years. The current challenge is to deliver leadership performance within a fixed power envelop and affordable cost structure.

Multi-core processors present several challenges over the next few years related to on-chip system architecture, power management, reliability, and software scaling. This talk will touch upon some of these challenges and discuss some possible solutions.

Dr. Dileep Bhandarkar is an IEEE Fellow, and a Distinguished Alumnus of the Indian Institute of Technology, Bombay, where he received his B. Tech in Electrical Engineering. He also has a M.S. and Ph.D. in Electrical Engineering from Carnegie Mellon University, and has done graduate work in Business Administration at the University of Dallas.

He is currently Director of Advanced Architecture in Intel's Digital Enterprise Group. His previous positions have included Director of Enterprise Microprocessor Architecture, Director of the Enterprise Architecture Lab, and Director of Strategic Planning for Intel Architecture processors and chipsets.

Prior to joining Intel in 1995, he spent almost 18 years at Digital Equipment Corporation, where he managed processor and system architecture, and performance analysis work related to the VAX, Prism, MIPS, and Alpha architectures. He also worked at Texas Instruments for 4 years in their research labs in a variety of areas including magnetic bubble memories, charge coupled devices, fault tolerant memories, and computer architecture.

Dr. Bhandarkar holds 15 U.S. Patents and has published more than 30 technical papers in various journals and conference proceedings. He is also the author of a book titled Alpha Implementations and Architecture: Complete Reference and Guide (Butterworth-Heinemann, 1996).

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