Virtual Global Communications
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As process technologies continue to improve, the number of transistors a designer can put on a chip is growing tremendously. Many techniques have been proposed by architects to use this extra space. However, many of the approaches make heavily-loaded broadcasts and long-distance wires a necessity. With the continued march into deep sub-micron (DSM) technologies, the challenge to architects is to design systems that operate efficiently in a world where global communication is expensive, due to both slower circuits and higher power consumption.
In response to this challenge, many architecture researchers have abandoned traditional architectures in an attempt to create new design paradigms from scratch which are based on only local communication. While these ideas have the possibility of avoiding communication complexity almost completely, they come at the momentous cost of redesigning every aspect of the computer, from chip units to compiler.
The goal of this work is to find and evaluate complexity-effective alternatives to global communication mechanisms in current-generation processors. Secondly, it is my goal to design these alternatives in such a way that they do not radically change the basic architecture of the machine. I call this goal design Virtual Global Communication.
In this dissertation, I examine several different specific communication bottlenecks. I then present possible solutions to reduce their communication complexity, remove them from critical timing paths, and reduce power consumption.
I explore the design space of dynamic instruction scheduling logic. I present a tag elimination mechanism and the Cyclone scheduler as methods for reducing and removing complex broadcast signals, respectively. Tag elimination is shown to reduce broadcast loading by up to 75%, while Cyclone is shown to provide competitive performance with a very fast broadcast-free circuit on a small chip footprint.