Michigan researchers win best paper award at DFT 2017

Prof. John Hayes and CSE graduate student Paishun Ting received the award for their paper entitled “Eliminating a Hidden Error Source in Stochastic Circuits.”

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John P. Hayes, Claude E. Shannon Professor of Engineering Science, and CSE graduate student Paishun Ting have received the Best Paper Award at the 30th IEEE Symposium on Defect and Fault Tolerance (DFT), which took place at Cambridge University in the UK October, 23-25, 2017.

Their paper is entitled “Eliminating a Hidden Error Source in Stochastic Circuits.”

Circuits that can rapidly sense and process streams of data that may include some uncertainty or change are extremely important in the development of learning machines, such as artificial vision systems and neural networks. Stochastic computing (SC) is “computing with probabilities” encoded in bit-streams, and it was designed for this type of application. SC continually operates and does not assume that hardware always produces the same results if given the same inputs.

Because they represent numerical values by streams of noise, stochastic circuits offer an entirely different perspective on computer arithmetics. They replace bulky multiplication and addition modules in conventional chips with single logic gates. Sums and products are computed by combining streams of digital noise and require sufficient time for statistical averages to reach expected values.

Advantages of typical SC circutits are their ultra-low power usage and small size, coupled with high error tolerance. However, due to its randomness features, SC’s accuracy is often low and hard to control, thus severely limiting its practical applications.

Over the last decade, Prof. Hayes and his students have developed a theory of such circuits, and in this paper have now addressed an important issue that arises in practice – if you compute with noise, some of the noise may be undesired. They now separate “good” noise from “bad” noise.

In their award paper, the researchers propose a systematic algorithm called Constant Elimination Algorithm for Suppression of Errors (CEASE) to eliminate unwanted noise by introducing memory into target circuits. They provide analytical and experimental results which demonstrate that CEASE is optimal in terms of minimizing unwanted noise.

DFT is an annual symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.

Paishun Ting is Graduate Student Research Assistant who works with Prof. Hayes. His research interests focus on statistical machine learning, hardware-accelerated deep neural networks, stochastic computing and GPGPU applications.

Prof. Hayes teaches and conducts research in the general area of computer science and engineering, with specific interests in computer hardware design, computer-aided design and testing, VLSI circuits, reliable computer architecture, and quantum computing. He earned his B.E. degree in electrical engineering from the National University of Ireland, Dublin, and his M.S. and Ph.D. degrees from the University of Illinois at Urbana-Champaign. He joined the faculty at Michigan in 1982; prior to that he was on the faculty of the University of Southern California. Prof. Hayes also worked in industry for a couple of years, and has held visiting positions at Stanford University, McGill University, the University of Montreal, Logicvision Inc., and the University of Freiburg.

Prof. Hayes was the founding director of Michigan’s Advanced Computer Architecture Laboratory, which is now known as the Computer Engineering Laboratory. He is author of seven books, including Computer Architecture and Organization, (McGraw-Hill, 3rd ed. 1998), Quantum Circuit Simulation (Springer, 2009) and Design, Analysis and Test of Logic Circuits under Uncertainty (Springer, 2012), as well as over 275 technical papers and several patents. He received the University of Michigan’s Distinguished Faculty Award in 1999, the Alexander von Humboldt Foundation’s Research Prize in 2004, and the IEEE Test Technology Council Lifetime Contribution Medal in 2013, and the ACM SIGDA Pioneering Achievement Award in 2014. Prof. Hayes is a Fellow of both IEEE and ACM.

Chip Design & Architectures; John Hayes; Research News