Computer Engineering Seminars

Innovating at the Intersection of Architecture and Emerging Workload Paradigms

Innovating at the Intersection of Architecture and Emerging Workload Paradigms

Let’s Go Sparse: Towards Sparse-Aware Computing System Design

SafeBet: A Simple, Secure and Fast Solution for Spectre and Meltdown

Generalizing the ISA to the ILA: A Software/Hardware Interface for Accelerator-rich Platforms

Towards General Purpose Specialization

Enabling Continuous Learning through Synaptic Plasticity in Hardware

Principled Secure Processor Design

A Graph-Based Dataflow Architecture for Executing Neural Networks

Getting Computer Systems Ready for Visual Computing in Ten Years

System and Architecture Design for Safe and Reliable Smart Applications

New Paradigms in Cache Architectures

Server Architecture for the Post-Moore Era

Harnessing Data Science for the HW Verification Process

Design and Synthesis of Approximate Computing Circuits

Chupja–PHY Covert Channels: Can you see the Idles?

Data Storage and Querying for Resource Constrained Computing Devices

Dynamic Hardware Resource Management for Efficient Throughput Processing

Physically Dense Server Architectures

Enabling dedicated single-cycle connections over a shared Network-on-Chip

Towards a Watt-Wise Web: Architecting for a Responsive and Energy-Efficient Mobile Web

Execution Stream Fingerprinting for Low-cost Safety-critical System Design

Economic Mechanisms for Managing Risk in Heterogeneous Datacenters

Practical Language and System Support for Reliable Concurrent Software

Cyber-Physical Systems: A Rehash or A New Intellectual Challenge?

Deriving Neurological Connectomes to Better Understand Complex Brain Functionality

Design for Security

Compilation for SPM-based Manycore Architectures

BigData and Dark Silicon: Taming Two IT Inflection Points on a Collision Course

Safe asynchronous event-driven programming in P

Operating system support for high-throughput processors

Cyber-Physical Systems at Small and Large Scales

Synthesis Problems for Reliable Clock Network Design

Optimizations for Cache-Coherent Networks-on-Chip

Disciplined Approximate Computing: From Language to Hardware

Efficient and Predictable Execution of Object-Oriented Code on the SHAP Platform

Evolving Methodologies in Electronic Design Automation

Its All about the Memory (again)

SST: A modelling framework integrating Gem5, DRAMSim, McPAT and other components

Moneta: Engineering Storage for the Data Age

GreenDroid: An Architecture for the Dark Silicon Era

Proportional Error Tolerance for Efficient and Effective Performance and Reliability

Run-time adaptive performance control and design issues in subthreshold SRAM

MINIX 3: A Reliable and Secure Operating System

Integrated Circuit Design at Aalto University Department of Micro and Nano Sciences

Programming models for the Barrelfish multi-kernel operating system

DLP Lecture: Ultra‐low power logic circuits: from voltage‐mode to current‐mode

Building Brains

Efficient Processor Fault Tolerance

Converging Architecture, Implementation, and Software Development through Parallelized Simulators

Designing Multicores for Programmability: The Bulk Multicore Architecture

Dynamic Thermal Estimation and Management in Nanoscale Systems

Exploiting Parallel Execution Models in OS Design – A Report on IBM Cyclops-64 System Software Model and Design

The Talking Book: a $10 Rural Audio Computer to Improve
Health and Literacy in Developing Countries

Scalable Montgomery Multipliers for Cryptography Accelerators

Secure Low-Level Programming via Hardware-Assisted Memory-Safe C

Threads Should Not Play Dice: Determinism and Bug Avoidance for Multithreaded Programs

Robust Computation with Subthreshold Leakage Currents

Low Voltage Circuit Design Techniques for 32nm and Beyond

Variations – and Aging Tolerant 6T SRAM Designs

Secure Vehicle-to-Vehicle Communication

Problem Solving in Visual Effects: Spider-Man 3

Design-for-reliability for scaled electronic technologies: Opportunities and challenges

Why Tools Matter

Combining Circuits + Architecture to Combat Variability in Nanoscale CMOS

A Non-Linear Neural Classifier and its Applications in Testing Analog/RF Circuits

Out-of-order processing-History of the IBM System/360 Mode 91

Multi-Core Chips for Networking and Security

Architectural Acceleration of Real-Time Physics

Log-based Transactional Memory

Design of Clock Distribution in High Performance Processors

Multi-Core Microprocessor Chips: Motivation & Challenges

The ARM MPCore multicore technology

Future CPU Architectures – The Shift from Traditional Models

Synthesis, Verification, and Test Reading Group

Computer Architecture Research: Some Criticisms and Some Opportunities

Niagara 2 and Paralleo Programing with Transactional Memory

Slaying Trolls: Market Based Patent Reform and High Tech Inventors

How Does Miss Clustering Affect The Cost of A Cache Miss

Decentralized Control and Optimization Techniques for Autonomic Performance Management of Distributed Computing Systems

Thermal Design and Gate Sizing for Fin FETs

Fault Diagnosis and Logic Debugging Using Boolean Satisfiability

Patents, and Their Importance to Computer Engineers

Designing NICs in CMT Environment

Crossbow – Network stack virtualization & Resource control

Fast Multilevel Logic Optimization using Local Transformations

Reading group: Synthesis, Verification and Test

Liberating Threads from Sequential Programs

Checkpointed Processor Architecture

Hardware and Software Design for 10 Gigabit Network Servers

Embedded Streaming Multimedia Computation with the RSVP(TM) Architecture

Transactional Coherence and Consistency (TCC)

The Pros and Cons of Very-Low-Voltage Testing

Defect Aware Tests

Voodoo – Architectural support for composing fast/secure software

Low-power interconnection networks

Designing Commercial Servers and Token Coherence

Resolution-Based Simplification Techniques of CNF Formulas

High speed CMOS transceivers for parallel optical interconnects

Challenges in the Evolution of Server-class Instruction-set Architectures

Efficient SAT-based Bounded Model Checking for Software Verification

Exploring the Limits of Prefetching

Next-Generation Wireless LAN Technology

Speculative Multithreading: from Multiscalar to MSSP

EV98-The Post-ultimate Alpha

Security Software Verification: (My) Past and Future

Analog Intellectual Property: What It Is,

Meet the ACAL Architecture/Compiler Faculty

Meet The ACAL CAD/VLSI Faculty